1. Field of the Invention
The present invention relates to an image scanner optically reading original images, and more particularly to an image scanner equipped with an AFE (Analog-Front-End) capable of driving at high speed. In addition, the present invention relates to an image forming apparatus such as digital copiers, facsimiles and digital multifunctional printers equipped with the image scanner. Further, the present invention relates to a sample hold control method used in the image scanner and the image forming apparatus.
2. Discussion of the Background
Accompanied with demands for images having higher quality at higher speed from image forming apparatus such as digital copiers, an image scanner installed in image forming apparatus is required to read images at higher pixel and higher speed. Therefore, a CCD (Charged Coupled Device) and an AFE (Analog-Front-End) in a scanner are required to drive at higher speed. The CCD photoelectrically converts light reflected from the original image, and the converted image signal is fed into the AFE to be subjected to a sample hold and an A/D conversion. When the CCD and the AFE are driven at high speed, it is necessary to ensure timing of the image signal produced from the CCD and a sample hold signal (hereinafter referred to as “SHD”) controlling the sample hold at the AFE.
As a method of ensuring timing of the image signal from the CCD and the sample hold signal, an invention disclosed in Japanese published unexamined application No. 11-177783 is known. The present invention has a CCD an original image is projected on while reduced and three sample hold circuits, which are driven on a same substrate. A CCD drive clock and a sample hold signal are fed through a same driver because an image signal from the CCD depends on a CCD drive signal. Therefore, the CCD drive signal and SHD, further the image signal from the CCD and a timing skew are reduced to ensure timing even when the CCD and the AFE are driven at high speed.
However, the CCD is driven at 5 V while the AFE at 3.3 v, and therefore an output of the driver cannot directly be used as the SHD and an amplitude is reduced with a partial pressure. Then, the AFE has an I/F of a different electric source regardless of the amplitude. Namely, since the SHD is independently fed from the AFE, when a driver electric source (5 V) and an AFE electric source (3.3 V) rise up in this order, an excess voltage is applied to the AFE, resulting in breakdown and deterioration of devices, and even destruction thereof in the worst case. This can be avoided with a diode inserted between the SHD and the AFE electric source, but a diode varies a reverse bias capacity so much that the CCD and the AFE are difficult to drive at high speed.
FIG. 10 is a block diagram illustrating a configuration of periphery of a CCD 4, a timing signal generator (TG) 3, a CCD driver (DRV) 6 and an AFE 5 of a conventional scanner 111. TG3 generates a CCD drive signal (CCD_CLK) and an AFE drive signal (SHD, MCLK). The CCD_CLK and SHD signals are fed to CCD 4 and AFE 5, respectively through the DRV 6. The MCLK needs to ensure a timing with the SHD fed from the DRV, however, it is not fed through the DRV 6 in FIG. 10 because the timing is easily ensured. Meanwhile, the CCD 4 produces an image signal (SIG), which is buffered by an output buffer (EF) 7 formed of an emitter follower and fed into the AFE 5 through an AC connection 8.
FIG. 11 illustrates a detail of a circuit configuration of periphery of the TG 3, CCD 4 and AFE 5 in FIG. 10. In FIG. 11, the voltage of the SHD of the AFE 5 is divided so as to become from DRV_VCC 5V to AFE_VCC 3.3 V (In FIG. 4, SIG is omitted).
FIG. 12 illustrates a relationships among the SHD of the AFE 5, the DRV_VCC 5V and the AFE_VCC 3.3 V in FIG. 11. As FIG. 12 shows, in a sequence where the DRV_VCC and the AFE_VCC rise up in this order when the apparatus is switched on and the AFE_VCC and the DRV_VCC shut down when the apparatus is switched off, the following status is present:
AFE_VCC: OFF
DRV_VCC: ON
Therefore, a period of a time lag between the rise up and the shut down (Tlag_on and Tlag_off) is a period when SHD applies an excess voltage to the AFE 5, an input rating of the AFE 5 such as VCC+0.5V cannot be satisfied. In the present invention, power-on and power-off mean power-on and power-off of a scanner or an image forming apparatus.
Because of these reasons, a need exists for a scanner avoiding an excess voltage to an AFE and having no limit to a sequence of power supply.